Digital design verification is a time and energy consuming task. In an attempt to streamline it, Accelera created UVM, which stands for Universal Verification Methodology. The UVM standard focuses on interoperability and Verification IP re-use. It can be summarized in 3 points:
Published: Friday, 31 August 2012 22:08
The benefits of UVM are:
- a methodology
- based on SystemVerilog (SV) but not limited to it
- a set of SV classes to support the methodology
“It exists, it is supported, it is well defined, there is no alternative.”
- Predictability : benchmarks can easily be defined
- Proven / Complete : used by many companies in many projects
- Independent / Open : not linked to a tool vendor
- Existing : do not re-invent the wheel
- Ease of maintenance : because standard and based on SV
- Reuse / Scalable : through verification components but also test cases
- Interoperable : verification assets can be reused (eVC)
Published: Tuesday, 05 June 2012 13:47
RTL simulations are used to observe the outputs of a design when the inputs are driven. The goal is to characterize the circuit and verify its functionality in all circumstances and conditions.
This article shows a few RTL simulation technics with their advantages and inconvenients. The first ones are outdated and do not address anymore the challenges of verification of complex design but they are still used because of legacy reasons or by lack of knowledge / time of the verification engineers. The last ones that include random verification and functional coverage are an introduction to what can be accomplished with state-of-the-art technics like OVM / UVM.
Published: Wednesday, 11 July 2012 13:41
The goal of static timing analysis (STA) is to verify that a particular digital design meets all timing constraints. Timing analysis firstly occurs during logic synthesis. It is also widely run between each step of the place-and-route flow.
The analysis is called static because it checks timing for signal paths between pairs of consecutive sequential elements or between I/O and first/last sequential element of the path.
Published: Thursday, 05 July 2012 13:43
Logic synthesis is the action of translating a high level description of a digital circuit into a netlist of logic gates and sequential elements (flip-flops, latches).
The literature concerning the logic synthesis process is abundant. It describes extensively the algorithms and methods used to generate combinatorial logic from eg truth table or how to convert RTL (Register Transfer Level) to mathematical expressions.
This article focuses on the logic synthesis seen from a user point-of-view and on what might go wrong during the process.
Published: Thursday, 24 January 2013 20:45
In this article Marco Cornero and Andreas Anyuru illustrate and compare the main technological options available in multiprocessing for mobile platforms, highlighting the synergies between multiprocessing and the disruptive FD-SOI silicon technology used in the ST-Ericsson products. They show that compared to personal computers (PCs), the performance of single-processors in mobile platforms is still growing and how, from a software performance perspective, it is more profitable today to focus on faster dual-core rather than slower quad-core processors.