Check Timing With VHDL Attributes

It is sometimes necessary to check for timing violations in a VHDL model or testbench. Here is a very nice overview from Mark Harvey, published on his blog

An essential part of any VHDL model written for simulation is checking for timing violations, for example, a micropocessor model should check its acknowledge input for setup and hold violations or a memory model should check the active pulse width of its chip select, output enable and write enable inputs. VHDL has several predefined signal attributes which can be used during simulation to perform timing checks such as pulse width violations, setup or hold violations, etc. (Mark Harvey)

See further at www.markharvey.info

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