Check Timing With VHDL Attributes

It is sometimes necessary to check for timing violations in a VHDL model or testbench. Here is a very nice overview from Mark Harvey, published on his blog

An essential part of any VHDL model written for simulation is checking for timing violations, for example, a micropocessor model should check its acknowledge input for setup and hold violations or a memory model should check the active pulse width of its chip select, output enable and write enable inputs. VHDL has several predefined signal attributes which can be used during simulation to perform timing checks such as pulse width violations, setup or hold violations, etc. (Mark Harvey)

Introduction to UVM

Digital design verification is a time and energy consuming task. In an attempt to streamline it, Accelera created UVM, which stands for Universal Verification Methodology. The UVM standard focuses on interoperability and Verification IP re-use. It can be summarized in 3 points:
  • a methodology
  • based on SystemVerilog (SV) but not limited to it
  • a set of SV classes to support the methodology
The benefits of UVM are:
  1. Predictability : benchmarks can easily be defined
  2. Proven / Complete : used by many companies in many projects
  3. Independent / Open : not linked to a tool vendor
  4. Existing : do not re-invent the wheel
  5. Ease of maintenance : because standard and based on SV
  6. Reuse / Scalable : through verification components but also test cases
  7. Interoperable : verification assets can be reused (eVC)
“It exists, it is supported, it is well defined, there is no alternative.”

RTL Verification

RTL simulations are used to observe the outputs of a design when the inputs are driven. The goal is to characterize the circuit and verify its functionality in all circumstances and conditions.

This article shows a few RTL simulation technics with their advantages and inconvenients. The first ones are outdated and do not address anymore the challenges of verification of complex design but they are still used because of legacy reasons or by lack of knowledge / time of the verification engineers. The last ones that include random verification and functional coverage are an introduction to what can be accomplished with state-of-the-art technics like OVM / UVM.

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