IC Logic Synthesis

Logic synthesis is the action of translating a high level description of a digital circuit into a netlist of logic gates and sequential elements (flip-flops, latches).

The literature concerning the logic synthesis process is abundant. It describes extensively the algorithms and methods used to generate combinatorial logic from eg truth table or how to convert RTL (Register Transfer Level) to mathematical expressions.

This article focuses on the logic synthesis seen from a user point-of-view and on what might go wrong during the process.

Logic synthesis is performed by a program called a logic synthesizer or simply synthesizer. All major CAD tool vendors proposes one. The purpose of a synthesizer is:

  • to map an RTL database (Verilog, VHDL, ...) on a set of wires and gates (we abusively include flip-flops in the term gates),
  • using pre-defined libraries of standard cells,
  • and by respecting a set of constraints.


RTL Synthesis

Libraries of standard cells

A library of standard cells is a set of combinatorial and sequential elements (AND gates, OR gates, flip-flops, …) developed for a specific technology. A particular cell, eg AND gate, is generally available multiple times with different optimizations in terms of timings, size, power, output drive strength.

The libaries are common for all designers using the same technology and centrally available. They are developped by the founder where the chips are processed.

Synthesis constraints

Constraints are the targets assigned to the synthesizer to drive the optimization of the netlist.


RTL Synthesis


The most important ones are area and timing constraints (input/output delays, clock frequencies, ...).

Depending on the target technology, constraints like maximum fanout, maximum transition time, maximum capacitance ... can be handled already by the synthesizer or hand over to the place-and-route tool.

Finally, depending on the application of the IC, constraints like leakage current or power dissipation may or may not be present.

If the constraints cannot be respected by the synthesizer, then designers should question their RTL design and sometimes the technology that they chose.

Respect of timing constraints is checked by running a Static Timing Analysis. This is the object of another article.

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