Static Timing Analysis

The goal of static timing analysis (STA) is to verify that a particular digital design meets all timing constraints. Timing analysis firstly occurs during logic synthesis. It is also widely run between each step of the place-and-route flow.

The analysis is called static because it checks timing for signal paths between pairs of consecutive sequential elements or between I/O and first/last sequential element of the path.

Propagation time

Consider the simple circuit in the next figure made of a logic path (in blue) between two flip-flops (FFs). The first flip-flop is called the launching FF and the second one is the capturing FF. Both of them work on the same clock of time period Tperiod.


Static Timing Analysis signal path


When the state of pin Q1 of the first flip-flop changes, it takes some time for the new state to propagate to pin D2 of the second flip-flop. This is called the propagation time of the signal (tprop). The propagation time depends on the:

  • combinatorial logic between the two flip-flops,
  • capacitive load of the wires that connects the combinatorial gates together and to the flip-flops.
  • characteristics of the incoming signal like transition time
  • operating conditions like temperature and voltage

In this simple example, the signal is launched by one clock edge and captured by the next clock edge. There is thus maximum 1 clock period available for the signal to propagate.

Setup and hold time

Synchronous elements like flip-flops have also their intrinsic constraints. We define the followings for the synchronous input D of a FF:

Setup time (tsetup) is the minimum amount of time the data signal (D) msut be held steady before the clock rising edge event so that the data is reliably sampled by the clock.

Hold time (thold) is the minimum amount of time the data signal (D) must be held steady after the clock rising edge so that the data is reliably sampled.


Static Timing Analysis setup hold


Note that similar constraints are defined for the asynchronous input of a flip-flop (like the reset/set pin). We then talk about recovery and removal time.

If those constraints are not respected then the Q output data of the flip-flop is undefined.

Basic principle of STA

A basic static timing analysis checks that propagation time of data through combinatorial logic is smaller than the clock period of the design and that all setup and hold time constraints are respected.

This can be summarized as:

Standard cells delay

The information necessary to calculate the delay of a combinatorial path is derived from the timimng information stored in the library of standard cells. Those libraries are characterized for different operating conditions with Spice simulations and silicon measurement.

The information on setup and hold time is also available in libraries.

Post-layout STA

Once the digital design is placed, routed and that all clock trees were synthesized, it is possible to extract from the layout all parasitics information of the wires (capacitance, resistance, ...) and to calculate the corresponding timings / delays.

The timing information of the wire delays is then used together with timing of standard cells derived from libraries to backannotate the design and run what is called a post-layout static timing analysis.

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