Static Timing Analysis

The goal of static timing analysis (STA) is to verify that a particular digital design meets all timing constraints. Timing analysis firstly occurs during logic synthesis. It is also widely run between each step of the place-and-route flow.

The analysis is called static because it checks timing for signal paths between pairs of consecutive sequential elements or between I/O and first/last sequential element of the path.

IC Logic Synthesis

Logic synthesis is the action of translating a high level description of a digital circuit into a netlist of logic gates and sequential elements (flip-flops, latches).

The literature concerning the logic synthesis process is abundant. It describes extensively the algorithms and methods used to generate combinatorial logic from eg truth table or how to convert RTL (Register Transfer Level) to mathematical expressions.

This article focuses on the logic synthesis seen from a user point-of-view and on what might go wrong during the process.

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