Reset Strategy

I was about to write a post on how to correctly handle the reset of a digital design when I hit this article on the subject.

Many design issues must be considered before choosing a reset strategy for an ASIC design, such as whether to use synchronous or asynchronous resets, will every flip-flop receive a reset, how will the reset tree be laid out and buffered, how to verify timing of the reset tree, how to functionally test the reset with test scan vectors, and how to apply the reset across multiple clocked logic partitions. (Clifford E. Cummings)

Have a look: Asynchronous and synchronous resets by Clifford E. Cummings presented at SNUG 2003 in Boston.

Topics being discussed in this paper are:

  • Flip-flops coding style
  • Synchronous resets
  • Asynchronous resets
  • Reset synchronizer
  • Reset distribution tree
  • Reset-glitch filtering
  • DFT aspects
  • Multi-clock reset issues