Automatic clock gating inference

Clock gating is a comon technique to reduce power consumption. There are two ways to gate clock in your design:
  1. manual clock gating
  2. automatic clock gating
See examples in this article. The first consists of manually gating the clock directly in your code. Care must be taken to correctly synchronize the enable signal on the falling edge of the clock to avoid minimum clock width violation:
  2. p_enable_synch : process(reset,clk) -- synchronization of the enable signal
  3. begin
  4. if (reset = '0') then
  5. en_s <= '0';
  6. elsif (clk'event and clk=0) then
  7. en_s <= en;
  8. end if;
  9. end process p_enable_sync
  11. gated_clk <= clk and en_s; -- manual clock gating
The second technique is called automatic clock gating because the cell that gates the clock is automatically inferred by the synthesis tool and is not present as such in the RTL. This is now a very common technique used by all major logic synthesiser. It is possible if a gating condition (also called recirculating multiplexer) can be identified in the RTL:
  2. p_gated_clock : process(reset,clk)
  3. begin
  4. if (clk'event and clk=1) then
  5. if (en = '1') then -- enable condition
  6. q <= d;
  7. end if;
  8. end if;
  9. end process p_gated_clock
Next picture shows the translation operated by the synthesis tool:

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