Issues in clock domain crossing

Clock domain crossing (CDC) is certainly one of the most frequent source of issues in digital IC design due to unproper handling, not enough attention or no good verification coverage.

There are many ways to deal with clock domain crossing.

The following article is one of the mostpopular on EETIMES EDA Designline : Understanding clock domain crossing issues by Saurabh Verma and Ashima S. Dabare, Atrenta. It deals with:

  • Metastability
  • Data loss
  • Data incoherency
  • Synchronous clocks with the same frequency and zero phase difference
  • Synchronous clocks with the same frequency and constant phase difference
  • Synchronous clocks with different frequency and variable phase difference (integer and rational multiuple clocks)
  • Asynchronous clock domain crossing
  • and of course the verification methodology...

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