IC packages

IC development is not only a story about silicon and how to design it. The package of an IC is also an important part of the final component and requires dedicated expertise. What is meant with IC packaging? It is basically the black plastic around the die of silicon and the (numerous) leadframe pins that attach it on a PCB.

 

Global view of an IC package

 

The two main goals of the package is:

  1. to protect the silicon die from aggressors like: human fingers, humidity, temperature, ...
  2. provide an interface between the silicon and the external world.
The general process of packaging can be summarised in 4 steps:
  1. Sawing of the wafers in multiple dice
  2. Attaching the silicon die to the die attach pad
  3. Wire bonding with gold wires between the die IOs and the leadframe pins of the package
  4. Molding the wire-bonded die with plastic (or ceramic)
but those different steps have evolved over time to constantly meet the request for lower cost PCB. Let's go through the history of the last years and review some of the major packages that exist.

DIP (Dual Inline Package)

PDIP
 
The DIP is perhaps the most known package. It is also the oldest one that could be easily plugged in a breadboard. Because it requires holes in the PCB to be mounted it is also known as through-hole package.
The fabrication process sticks well to the general description above. The plastic of the package has a rectangle shape and it features two rows of pins.

SOP (Small Outline Package)

SOP
 
The SOP is a surface-mounted package. This means that it does not require any holes in the target PCB and can be directly soldered on the surface of the PCB. This reduces the global cost of the PCB production. The SOP is 30-40% smaller than the equivalent DIP.
The fabrication process is also well in line with the global description.
Surface-mounted packages further evolved as TSOP (Thin Small Outline Package) with very low-profile and tight lead spacing and POWERSOP that are tailored for a better power dissipation.

BGA (Ball Grid Array)

With the increase of IC complexity came the request for more pins. As an example, an FPGA can count thousands of IOs. Using packages where pins are disposed along the sides of the package was not possible anymore. BGA packages do not have pins anymore but well balls arranged in a matrix under the package. This allows to have interconnections on the complete surface of the package.
 

Ball matrix of a BGA package

 
The balls are made of solder and are attached to a laminated substrate at the bottom side of the package. The substrate (on which the die is attached) acts a an extra layer of routing to route the terminations of the wire bonds to the balls. Note that flip-chip connection are possible instead of wirebonding.
A BGA is mounted on a PCB with copper pads in a arranged in a matrix that matches the solder balls. The soldering is made by melting the balls of the BGA in the heat of an oven.

CSP (Chip-Scale Package)

The need to spare board area lead to develop package that are approximately as large as the die. They are called chip-scale packages.
 

CSP

 
In order to qualify as chip scale, the package must have an area no greater than 1.2 times that of the die and it must be a single-die, direct surface mountable package.

WLCSP (Wafer-Level Chip Scale Package)

 
WLCSP
 
 
In case of WLCSP, the balls are deposited directly on the die and there is no plastic around the die to protect it.

MCP (Multi-Chip Package)

 

MCP

 
As the name indicates, a Multi-Chip Package encloses more than one die of silicon. A good example is the STLC2593 from STMicroelectronics that contain a Bluetooth die and a FM radio die plus some passive elements inside the same plastic package.
 
The dice can be located one next to the other or stacked.
 
MCP examples
 
The substrate of the package acts as a mini PCB to connect the dice to leadframe pins or balls but also to interconnect them together.
 
The primary target of such a package is again to reduce the PCB footprint.
 

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