Embedded programmers often get stuck coding around an awkward hardware design. These tips for hardware designers promise hope, and more efficient systems to boot.
Published: Wednesday, 25 March 2015 22:06
Involving the software team in the hardware design phase is the most logical solution, but is often impractical due to scheduling, funding, and staffing concerns. A reasonable alternative is to generate a set of hardware interface guidelines that will produce hardware designed to accelerate the software development process. Understanding the optimal hardware interface from the software developer's point of view prevents the creation of unnecessary process. Read more: Software-Friendly Hardware
Clock gating is a comon technique to reduce power consumption. There are two ways to gate clock in your design:
Published: Friday, 20 March 2015 22:39
See examples in this article.
- manual clock gating
- automatic clock gating
Published: Friday, 12 September 2014 23:30
Clock domain crossing (CDC) is certainly one of the most frequent source of issues in digital IC design due to unproper handling, not enough attention or no good verification coverage.
There are many ways to deal with clock domain crossing.
Published: Monday, 04 February 2013 13:39
I was about to write a post on how to correctly handle the reset of a digital design when I hit this article on the subject.
Many design issues must be considered before choosing a reset strategy for an ASIC design, such as whether to use synchronous or asynchronous resets, will every flip-flop receive a reset, how will the reset tree be laid out and buffered, how to verify timing of the reset tree, how to functionally test the reset with test scan vectors, and how to apply the reset across multiple clocked logic partitions. (Clifford E. Cummings)
Published: Wednesday, 19 February 2014 23:08
It is sometimes necessary to check for timing violations in a VHDL model or testbench. Here is a very nice overview from Mark Harvey, published on his blog
An essential part of any VHDL model written for simulation is checking for timing violations, for example, a micropocessor model should check its acknowledge input for setup and hold violations or a memory model should check the active pulse width of its chip select, output enable and write enable inputs. VHDL has several predefined signal attributes which can be used during simulation to perform timing checks such as pulse width violations, setup or hold violations, etc. (Mark Harvey)